With rapid development of semiconductor industry, Power Integrated Circuit (PIC) has being used in multiple fields, such as a motor control, a panel display drive control, and a control of driving computer peripheral equipment. Among the power devices adopted in the PIC, a high voltage device, Lateral Double Diffused MOSFET (LDMOS), is paid more attention due to its characteristics of high working voltage, simple technology, facilitation for compatible with low voltage Complementary Metal Oxide Semiconductor (CMOS) circuit in technology and the like. However, for semiconductor high voltage power device made of material of Si, the forward on-resistance of the LDMOS device is greater than that of the Vertical Double Diffused MOSFET (VDMOS), and the greater the forward on-resistance, the larger the dimension of the device. Thus, the manufacturing cost is increased.
Referring to FIG. 1, which is a schematic structural diagram of a conventional LDMOS device, the LDMOS device includes a substrate 1, an epitaxial layer 2, a drift region 3, a drain region 4, a well region 5, a source region 6, an oxide layer 7, a source 8, a gate 9, a drain 10 and a substrate electrode 15. In the case that the LDMOS device is of n type, the substrate 1 and the well region 5 are of p type, the epitaxial layer 2 is of n type, the drift region 3 is of n− type, and the drain region 4 and the source drain 6 are of n+ type. In the case that the LDMOS device is of p type, the substrate 1 and the epitaxial layer 2 are of p type, the well region 5 is of n type, the drift region 3 is of p− type, and the drain region 4 and the source drain 6 are of p+ type. The drift region 3 for enduring the voltage endurance in the LDMOS needs to be lightly doped. On the other hand, to decrease the forward on-resistance of the LDMOS device, the drift region 3, as a current channel, needs to be heavily doped. This results in the contradiction between the breakdown voltage BV and the on-resistance Ron. Taking the common Metal-Oxide-Semiconductor (MOS) device as an example, the relation between the breakdown voltage BV and the on-resistance Ron are as follows:
            R      on        =                            L          D                          q          ⁢                                          ⁢                      μ            n                    ⁢                      N            D                              =              5.39        ×                  10                      -            9                          ⁢                              (            BV            )                    2.5                ⁢                                  ⁢                  (                      for            ⁢                                                  ⁢            N            ⁢                          -                        ⁢            type            ⁢                                                  ⁢            MOS                    )                                R      on        =                            L          D                          q          ⁢                                          ⁢                      μ            p                    ⁢                      N            D                              =              1.63        ×                  10                      -            8                          ⁢                              (            BV            )                    2.5                ⁢                                  ⁢                  (                      for            ⁢                                                  ⁢            P            ⁢                          -                        ⁢            type            ⁢                                                  ⁢            MOS                    )                    Where LD is the length of the drift region, ND is the concentration of the drift region, μn and μp are the mobility of the electron and the hole respectively, and q is the electron charge. As can be seen, the on-resistance of the MOS device is directly proportional to the length of the drift region, and is inversely proportional to the concentration of the drift region. That is to say, the shorter the length or the higher the concentration, the smaller the on-resistance. As one of the MOS devices, the LDMOS device has the common characteristic of the MOS device. Therefore, to ensure certain voltage endurance, the length of the drift region 3 of the LDMOS device should not be designed to be too short; and the concentration thereof should not be designed to be too high, otherwise breakdown may occur nearby the PN junction of the well region 5 under the gate 9, decreasing the inverse voltage endurance of the LDMOS device.